Speaker
Fitzpatrick, Conor
(CERN)
Description
The LHCb experiment uses a triggerless readout system where its first stage (HLT1) is implemented on GPU cards. The full LHC event rate of 30 MHz is reduced to 1 MHz using efficient parallellisation techniques in order to meet throughput requirements. The GPU cards are hosted in the same servers as the FPGA cards receiving the detector data which reduces the network to a minimum. In this talk, the commissioning of this heterogeneous architecture using the first Run 3 data is presented.
| Consider for long presentation | No |
|---|
Primary authors
Santana Rangel, Murilo
(Universidade Federal do Rio de Janeiro)
Fitzpatrick, Conor
(CERN)
