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FPGA-based real-time cluster finding for the LHCb silicon pixel detector

May 11, 2023, 12:15 PM
Marriott Ballroom VII (Norfolk Waterside Marriott)

Marriott Ballroom VII

Norfolk Waterside Marriott

235 East Main Street Norfolk, VA 23510


Bassi, Giovanni (SNS and INFN Pisa)


We report the implementation details, commissioning results, and physics performances of a two-dimensional cluster finder for reconstructing hit positions in the new vertex pixel detector (VELO) that is part of the LHCb Upgrade. The associated custom VHDL firmware has been deployed to the existing FPGA cards that perform the readout of the VELO and fully commissioned during the start of LHCb Run 3 data taking. This work represents a further enhancement of the DAQ system, reconstructing VELO hits coordinates on-the-fly, in real time, at the LHC collision rate, and it is part of a wider effort aimed at boosting the real-time processing capability of HEP experiments by delegating intensive tasks to dedicated computing accelerators deployed at the earliest stages of the data acquisition chain. The end result is a DAQ throughput increase in excess of 11%, together with a corresponding drop in electrical power consumption, as the FPGA implementation requires O(50x) less power with respect to the GPU implementation. The tracking performance of this novel system being indistinguishable from a full-fledged software implementation, allows the raw pixel data to be dropped immediately at the readout level, yielding the additional benefit of a 14% reduction in data flow.

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Primary authors

Bassi, Giovanni (SNS and INFN Pisa) Giambastiani, Luca (INFN Padova and University of Padova) Hennessy, Karol (University of Liverpool) Lazzari, Federico (INFN Pisa and Università di Pisa) Morello, Michael Joseph (SNS and INFN Pisa) Pajero, Tommaso (University of Oxford) Passaro, Daniele (SNS and INFN Pisa) Fernandez Prieto, Antonio (IGFAE) Punzi, Giovanni (INFN Pisa and Università di Pisa)

Presentation materials